Polymorphic AES Encryption Implementation

This paper presents a hybrid hardware-software implementation of the AES encryption algorithm on the MOLEN polymorphic processor [1]. In order to combine the advantages of both the software and the hardware implementations, the application code has been divided into two computational approaches, software and hardware. Only the main ciphering function, the more computational demanding component, has been implemented in hardware in a Virtex II pro-20. The AES encryption core occupies about 20% of the available slices and utilizes 12 BRAMs. The proposed design is capable of running at a frequency above 100MHz. Even in the worst case scenario, where only one 128-bit block is encrypted, this implementation has a speedup of 43, compared to a pure software implementation running on a PowerPC at 300MHz. When encrypting a file of 16 kbits, the overhead of passing the data into the hardware (including the 1408 bits of the expanded key) is much less significant, thus a speedup of 569 times is obtained for the proposed design compared to the pure software implementation. This speedup corresponds to an increase on the encryption rate from 1.85 Mbits/s, for pure software, to 1057 Mbits/s in the polymorphic processor.